Framos, a provider of imaging and vision technology, has launched the first SLVS-EC RX IP Core for easy sensor interfacing with FPGAs from Xilinx. The proprietary Framos FPGA module, available with an evaluation kit, connects Sony’s latest high-speed SLVS-EC interface with Xilinx FPGAs and enables vision engineers to seamlessly upgrade to Sony’s interface technology. The Framos IP product provides the technological basis for future camera developments and embedded vision devices.

The Framos-developed RX IP Core reduces overhead and complexity implementing a Sony imager with SLVS-EC. As on-chip function block connecting the customer’s FPGA logic with the image sensor’s data stream, the IP Core receives the interface data, manages the byte-to-pixel conversion for various lane configurations and thus prepares a highly efficient processing workflow run on the FPGA. The Framos software supports SLVS-EC v1.2 with 1, 2, 4, 8 lanes configurable by the user and delivers pixels formats from 8 to 14-bit of raw data. By de-risking the sensor implementation it significantly reduces the development efforts and accelerates the time to market.

As an official Xilinx partner, Framos is working in close cooperation with Xilinx. The SLVS-EC RX IP Core works with the main existing and upcoming FPGA families. The package includes the encrypted RTL IP Core with a simulation environment (ModelSim) and dedicated reference design examples. The available evaluation kit provides designs to guide and test the implementation of a SLVS-EC-based sensor, including the HW/SW environment and documented implementation examples with source codes.